1. Technical Field
Example embodiments of the present invention relate to a wire structure and a forming method of the same, and in particular, to a wire structure having a multilayer wire structure which is formed in accordance with a Damascene method using copper, where electromigration resistance and stress migration resistance is increased, as well as a forming method of such a wire structure.
2. Description of the Related Art
Together with the miniaturization of semiconductor devices, wires have also become miniaturized, and as a result, wire resistance and capacitance between wires has increased, and a wire material having a lower resistance has come to be required, in order to increase the speed of the device. Therefore, copper of which the resistance is lower than that of aluminum and which is excellent in electromigration resistance is used as the wire material.
It is difficult to process copper in accordance with a conventional dry etching method, and it is necessary to form wires in accordance with a Damascene method, where a trench for copper wire is formed in advance in an insulating layer, a metal film is formed on the entire surface in such a manner that this trench is filled with the metal film, and the metal film on the insulating layer is removed in accordance with a chemical mechanical polishing method (CMP method) in such a manner that the metal film remains only in the trench. This method is reported in “PLANAR COPPER-POLYIMIDE BACK END THE LINE INTERCONNECTIONS FOR ULSI DEVICES,” Proceedings of 10th international VMIC, pp 15-21, 1993, by B. Luther et al. Here, copper is used together with polyimide.
Recently, a dual Damascene method, according to which via holes for connecting the first wire and the second wire and the second trench are simultaneously filled in at the same time, has particularly been used in order to further shorten the process. This method is disclosed in Japanese Unexamined Patent Publication 2001-160590 (conventional art 1) and the like. In the following, a general dual Damascene method is described.
First, as shown in FIG. 10(a), an etching stopping film 801 made of Si3N4 is formed on a semiconductor substrate 800. A first insulating layer 802 made of a fluorine added silicon oxide film (FSG film) is formed on top of this etching stopping film 801 in accordance with a chemical vapor deposition method (CVD method). A first trench 803 is formed in this first insulating layer 802 in accordance with a photo etching technology. Next, as shown in FIG. 10(b), a first diffusion preventing film 804 made of TaN and a copper seed film are formed on the inner surface of the first trench 803 in accordance with a physical vapor deposition method (sputtering method). After that, a copper film is formed on the first insulating layer 802 so as to fill in the trench 803 in accordance with an electrolytic plating method. The copper film on the first insulating layer 802 is removed in accordance with a CMP method, so that a first wire 805 is formed within the trench 803.
Subsequently, as shown in FIGS. 10(c) and 10(d), an interlayer diffusion preventing film 806 made of Si3N4 is formed on the gained substrate in accordance with a CVD method, and a second insulating layer 808 made of an FSG film is formed on this interlayer diffusion preventing film 806. Next, as shown in FIGS. 10(e) and 10(f), a resist mask 815 in a predetermined form is formed on the second insulating layer 808, and a via hole 809 is formed in the second insulating layer 808 by means of dry etching so as to reach the interlayer insulating layer 806. After that, the resist mask 815 is removed.
Next, as shown in FIGS. 10(g) and 11(a), a resist mask 817 in a predetermined form having an opening above the via hole 809 is formed on the second insulating layer 808, and a second trench 810 is formed by means of dry etching so as to continue to the via hole 809. After that, the resist mask 817 is removed. Next, as shown in FIG. 11(b), the interlayer diffusion preventing film 806 on the first wire 805 is removed by means of dry etching using the second insulating layer 808 as a mask, so that the first wire 805 is exposed. Furthermore, as shown in FIGS. 11(c) and 11(d), a second diffusion preventing film 812 made of TaN and a copper seed film are formed on the gained substrate in accordance with a sputtering method. A copper film 813 is formed in accordance with an electrolytic plating method so as to have such a film thickness that the via hole and the second trench are completely filled in. The copper film 813 and the second diffusion preventing film 812 on the second insulating film 808 are removed in accordance with a CMP method, and thereby, a conductor and a second wire, which form a dual Damascene wire, are formed within the via hole and the second trench.
In the wire structure that has been formed in accordance with a dual Damascene method according to this conventional art 1, however, the second diffusion preventing film 812, which has been formed on each side walls of the via hole 109 and the second trench 110 (sides of the second insulating film 808) in accordance with a sputtering method, has a deposited film thickness of as small as approximately 3 nm, and discontinuous portions, and thus has a disadvantageous structure in terms of electromigration resistance and stress migration resistance (see FIG. 11(c)). In addition, the copper on the surface of the first wire 805 that has been removed by means of dry etching for the interlayer diffusion preventing film 806, as illustrated in FIG. 11(b) adheres to sides of the second insulating layer 808 in the vicinity of a bottom of the via hole 809. This causes a risk that electromigration may deteriorate.
In recent years, a method for making a thick diffusion preventing film adhere to side walls at the bottom of a via hole (resputtering method) is adopted when a diffusion preventing film is formed after the formation of a via hole and a trench, in order to solve the above described problem with the conventional art 1. This method is disclosed in Japanese Unexamined Patent Publication 2004-153162 (conventional art 2). In the following, the resputtering method is described.
In this conventional art 2, first, as shown in FIGS. 12(a) and 12(b), a via hole 909 and a second trench 910 are formed above the first wire 905 and the first insulating layer 902, in the same manner as in the general dual Damascene method according to the conventional art 1. The interlayer diffusion preventing film 906 made of Si3N4 on the first wire 905 is dry etched, so that the first wire 905 is exposed.
After that, as shown in FIGS. 12(d) and 12(e), a second diffusion preventing film 912 made of TaN is formed in accordance with a sputtering method. Sputtering etching is carried out on the second diffusion preventing film 912 on the bottom of the via hole 909 by applying an RF bias, and TaN 912a, which is the material that forms the second diffusion preventing film 912 and is removed through etching, is made to adhere to the side walls at the bottom of the via hole 909. Subsequently, as shown in FIG. 12(f), a third diffusion preventing film 913 made of TaN is laminated on the second diffusion preventing film 912, so that the side walls of the via hole 909 and the second trench 910 are coated with a diffusion preventing laminated film having a large film thickness. After that, a copper seed film is formed on the third diffusion preventing film 913 in accordance with a sputtering method. A copper film 914 is formed in accordance with an electrolytic plating method so as to have such a film thickness that the via hole and the second trench are completely filled in. The copper film 914, the third diffusion preventing film 913 and the second diffusion preventing film 912 are removed in accordance with a CMP method, so that a conductor and a second wire which form a dual Damascene wire are formed within the via hole and the second trench.
In accordance with the resputtering method of this conventional art 2, however, as shown in FIG. 12(c), the interlayer diffusion preventing film 906 made of Si3N4 is dry etched down to the surface of the first wire 905 made of copper, and therefore, copper adheres to the sides of the second insulating layer 905 in the vicinity of the bottom of the via hole 909. As a result of this, there is a possibility that copper may diffuse into the second insulating film 908, and electromigration resistance and stress migration resistance may be deteriorated. Here, in FIG. 12(c), arrows above the first wire 905 indicate a state where copper adheres to the sides of the second insulating layer 908 (regions circled by dotted ovals).